1 features two regulated outputs primary output 5v 5%; 500ma secondary standby 5v 5%; 10ma low dropout voltage (0.6v at 0.5a) on/off control option low quiescent drain (<3ma) reset option protection features reverse battery 60v load dump -50v reverse transient short circuit thermal shutdown overvoltage shutdown package option 5 lead to-220 tab (gnd) 1 cs8135 5v, 5v low dropout dual regulator with /enable reset cs8135 description block diagram absolute maximum ratings 1v in 2v out1 3 gnd 4/ enable 5v out2 reset december, 2001 - rev. 3 on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com archive device not recommended for new design the cs8135 is a low dropout, high cur- rent, dual 5v linear regulator. the sec- ondary 5v /10ma output is often used for powering systems with standby memory. quiescent current drain is less than 3ma when supplying 10ma loads from the standby regulator. in automotive applications, the cs8135 and all regulated circuits are protected from reverse battery installations, as well as two-battery jumps. during line transients, such as a 60v load dump, the 500ma output will automatically shut down the primary output to pro- tect both internal circuits and the load. the standby regulator will continue to power any standby load. the cs8135 is packaged in a 5 lead to-220. note: the cs8135 is compatible with the lm2935. input voltage operating range .....................................................................-0.5v to 26v load dump ............................................................................................60v internal power dissipation ..................................................internally limited junction temperature range (t j )............................................-40? to +150? storage temperature range ....................................................-65? to +150? lead temperature soldering wave solder (through hole styles only)..........10 sec. max, 260? peak electrostatic discharge (human body model) ..........................................2kv v in v out2 gnd v out1 reset/ enable output current limit + - output current limit over voltage shutdown + - + - primary output standby output + - thermal shutdown bandgap reference
2 cs8135 parameter test conditions min typ max unit electrical characteristics : v in = 14v, i out1 = 5ma, i out2 = 1ma, -40? t a 125?, -40? t j 150? unless otherwise specified output stage (v out1 ) output voltage, v out1 6v v in 26v, 5ma i out1 500ma 4.75 5.00 5.25 v dropout voltage i out = 500ma 0.35 0.60 v i out = 750ma 0.50 v line regulation 6v v in 26v, i out1 = 5ma 10 50 mv load regulation 5ma i out 500ma 10 50 mv quiescent current i out1 10ma, no load on standby 3 7 ma i out1 = 500ma, no load on standby 30 100 ma i out1 = 750ma, no load on standby 60 150 ma ripple rejection f = 120hz 66 db current limit 0.75 1.40 a maximum line transient v out1 5.5v 90 v reverse polarity v out1 -0.6v, 10 ? load -50 v input voltage, dc reverse polarity input 1% duty cycle, t = 100ms, v out1 -6v, -80 v voltage, transient 10 ? load output noise voltage 10hz-100khz 100 vrms long term stability 20 mv/khr output impedance 500ma dc and 10ma rms, 200 m ? 100hz-10khz overvoltage shutdown 30 v standby output (v out2 ) output voltage (v out2 ) 6v v in 26v, 1ma i out1 10ma 4.75 5.00 5.25 v dropout voltage i out2 = 10ma 0.3 0.7 v tracking v out1 - v out2 50 200 mv line regulation 6v v in 26v 4 50 mv load regulation 1ma i out1 10ma 10 50 mv quiescent current i out 10ma, v out off 2 3 ma ripple rejection f = 120hz 66 db current limit 25 70 ma output noise voltage 10hz-100khz 300 v long term stability 20 mv/khr output impedance 10ma dc and 1ma rms, 100hz-10khz 1 ? function output voltage low r 1 = 20k ? , v in = 4.5v see test & application circuit 0.8 1.1 v high r 1 = 20k ? , v in = 14v (page 6) 4.5 5.0 6.0 v output current v in = 4.5v, in low state 5 ma on/off resistor r1 ( 10% tolerance) 20 30 k ? reset reset reset reset
3 cs8135 package lead description package lead # lead symbol function typical performance characteristics to-220 1v in supply voltage to ic, usually direct from battery. 2v out1 regulated output voltage 5v, 500ma (typ) switched. 3 gnd ground connection. 4 /enable cmos compatible output lead, goes low whenever v out1 becomes unregulated. to use the enable option, con- nect the lead via a resistor to v in (see app. notes). 5v out2 standby output 5v, 10ma typ, always on. reset reset dropout voltage vs. output current standby dropout voltage vs. output current output voltage vs. input voltage standby output voltage vs. input voltage line transient response (v out1 ) line transient response (v out2 ) 10 time ( s) input voltage change (v) output voltage deviation (mv) 5 0 -5 -10 3 2 1 0 0102030405060 20 10 0 -10 -20 3 2 1 0 0 10 20 304050 60 time ( s) input voltage change (v) output voltage deviation (mv) i out 1 =500ma 7 6 5 4 3 2 1 0 -1 -2 -40 -20 0 20 40 60 input voltage (v) output voltage (v) r l =500 ? 7 6 5 4 3 2 1 0 -1 -2 -40 -20 0 20 40 60 input voltage (v) output voltage (v) r l =10 ? 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 input-output differential voltage (v) output current (ma) 0 5 101520 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 input-output differential voltage (v) output current (ma) 0 200 400 600 800
load transient response (v out1 ) load transient response (v out2 ) quiescent current vs. output current quiescent current vs. standby output current maximum power dissipation (to-220) ambient temperature ( c) power dissipation (w) 20 0 18 16 14 12 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 infinite heat sink 10 c/w heat sink no heat sink standby output current (ma) quiescent current (ma) 0 5 4 3 2 1 0 5 10 15 20 25 switch open v o off output current (ma) quiescent current (ma) 0 120 100 80 60 40 20 0 200 400 600 800 i out2 =10ma 150 time ( s) standby load current (ma) standby output voltage deviation (mv) 100 50 0 -50 -100 -150 20 15 10 5 0 0 10 2030405060 150 time ( s) load current (a) output voltage deviation (mv) 100 50 0 -50 -100 -150 0.8 0.6 0.4 0.2 0 0 102030405060 4 typical performance characteristics: continued cs8135
v in switch v out 1 reset v out 2 system condition 5v 0v 0v open 14v 5v 5v 60v 31v 3v 2.4v 26v closed 5v 0v 2.4v turn on load dump low v in line, noise, etc. v out1 short circuit thermal shutdown turn off 5v 5v 5v 0v open 14v 5v typical circuit waveform *reference test & application circuit the cs8135 is equipped with two outputs. the second out- put is intended for use in systems requiring standby mem- ory circuits. while the high current regulator output can be controlled with the lead described below, the stand- by output remains on under all conditions as long as suffi- cient input voltage is applied to the ic. thus, memory and other circuits powered by this output remain unaffected by positive line transients, thermal shutdown, etc. the standby regulator circuit is designed so that the quies- cent current to the ic is very low (<3ma) when the other regulator output is off. in applications where the standby output is not needed, it may be disabled by connecting a resistor from the standby output to the supply voltage. this eliminates the need for a capacitor on the output to prevent unwanted oscilla- tions. the value of the resistor depends upon the mini- mum input voltage expected for a given system. since the standby output is shunted with an internal diode zener, the current through the external resistor should be suffi- cient to bias v out2 up to this point. approximately 60 a will suffice, resulting in a 10k ? external resistor for most applications. reset standby output 5 circuit description cs8135 dropout voltage the input-output voltage differential at which the circuit ceases to regulate against further reduction in input volt- age. measured when the output voltage has dropped 100mv from the nominal value obtained at 14v input, dropout voltage is dependent upon load current and junc- tion temperature. input voltage the dc voltage applied to the input with respect to ground. input output differential the voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate. line regulation the change in output voltage for a change in the input voltage. the measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. load regulation the change in output voltage for a change in load current at constant chip temperature. long term stability output voltage stability under accelerated life-test condi- tions after 1000 hours with maximum rated voltage and junction temperature. output noise voltage the rms ac voltage at the output, with constant load and no input ripple, measured over a specified frequency range. quiescent current the part of the positive input current that does not con- tribute to the positive load current. i.e., the regulator ground lead current. ripple rejection the ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. temperature stability of v out the percentage change in output voltage for a thermal variation from room temperature to either temperature extreme. current limit peak current that can be delivered to the output. definition of terms
6 cs8135 application notes the output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr, can cause insta- bility. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low tem- peratures (-25? to -40?), both the value and esr of the capacitor will vary considerably. the capacitor manufac- turers data sheet usually provides this information. the value for output capacitor c 2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. to determine acceptable values for c 2 and c 3 for a partic- ular application, start with a tantalum capacitor of the rec- stability considerations s1 on/off reset flag r 1 20k ? c1* 0.1 f reset/ enable v in v out1 gnd v out2 c3** 10 f + + 10 f c2 ** cs8135 notes: * c1 required if regulator is located far from power supply filter. ** c2, c3 required for stability. test & application circuit disabling v out2 when it is not needed. c3 is no longer needed. unlike the standby regulated output, which must remain on whenever possible, the high current regulated output is fault protected against overvoltage and also incorporates thermal shutdown. if the input voltage rises above approx- imately 30v (e.g., load dump), this output will automatical- ly shutdown. this protects the internal circuitry and enables the ic to survive higher voltage transients than would otherwise be expected. thermal shutdown is effec- tive against die overheating since the high current output is the dominant source of power dissipation in the ic. the function has the ability to serve a dual purpose if desired. when controlled in the manner shown in the test circuit (common in automotive systems where /enable is connected to the ignition switch), the lead also serves as an output flag that is active low when- ever a fault condition is detected with the high current regulated output. under normal operating conditions, the output voltage of this lead is high (5v). this is set by an internal clamp. if the high current output becomes unreg- ulated for any reason (line transients, short circuit, thermal shutdown, low input voltage, etc.) the lead switches to the active low state, and is capable of sinking several mil- liamps. this output signal can be used to initiate any reset or start-up procedure that may be required of the system. the lead can also be driven directly from logic cir- cuits. the only requirement is that the 20k ? pull-up resis- tor remain in place. this will not affect the logic gate since the voltage on this lead is limited by the internal clamp to 5v. the signal is sacrificed in this arrangement since the maximum sink capability of the lead in the active low state (approximately 5ma), is usually not sufficient to pull down the active high logic gate. the flag can be retained if the driving gate is open collector logic. controlling on/off terminal with a typical cmos or ttl logic gate reset pulse on power-up (with approximately 300ms delay) reset/ enable gnd cs8135 r1 20k ? r2 100k ? 4.7 f cmos mm 74co4 or equivalent delayed reset out cs8135 v in r1 20k ? reset/ enable reset reset reset reset reset function high current output v in v out 2 r d 10k ? c 3 + v out 2 circuit description: continued
7 cs8135 application notes: continued ommended value and work towards a less expensive alternative part for each output. step 1: place the completed circuit with the tantalum capacitors of the recommended values in an environmen- tal chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with capacitor c 2 will simulate the higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load on the output under observation and look for oscillations on the output. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the output at low temperature. step 4 : maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage condi- tions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capaci- tor will usually cost less and occupy less board space. if the output oscillates within the range of expected operat- ing conditions, repeat steps 3 and 4 with the next larger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: remove the unit from the environmental chamber and heat the ic with a heat gun. vary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regula- tor performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temper- atures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. repeat steps 1 through 7 with the capacitor on the other output, c 3 . the maximum power dissipation for a dual output regu- lator (figure 1) is: p d(max) = {v in(max) -v out1(min) }i out1(max) + {v in(max) -v out2(min) }i out2(max) +v in(max) i q (1) where v in(max) is the maximum input voltage, v out1(min) is the minimum output voltage from v out1 , v out2(min) is the minimum output voltage from v out2 , i out1(max) is the maximum output current for the application, i out2(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permis- sible value of r ja can be calculated: r ja = (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja 's less than the calculated value in equation 2 will keep the die temperature below 150?. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 1: dual output regulator with key performance parameters labeled. a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja . r ja = r jc + r cs + r sa (3) where r jc = the junction-to-case thermal resistance, r cs = the case-to-heatsink thermal resistance, and r sa = the heatsink-to-ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the inter- face between them. these values appear in heat sink data sheets of heat sink manufacturers. heat sinks v in smart regulator v out 1 i out 1 i in i q control features } v out 2 i out 2 150? - t a p d calculating power dissipation in a dual output linear regulator
part number description cs8135yt5 5 lead to-220 straight cs8135ytva5 5 lead to-220 vertical cs8135ytha5 5 lead to-220 horizontal 8 cs8135 ordering information package thermal data package dimensions in mm (inches) thermal data 5 lead to-220 r jc typ 2.3 ?/w r ja typ 50 ?/w package specification 5 lead to-220 (t) straight 2.87 (.113) 2.62 (.103) 6.93(.273) 6.68(.263) 9.78 (.385) 10.54 (.415) 1.02(.040) 0.63(.025) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 6.55 (.258) 5.94 (.234) 14.22 (.560) 13.72 (.540) 1.02 (.040) 0.76 (.030) 3.71 (.146) 3.96 (.156) 14.99 (.590) 14.22 (.560) on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000 archive device not recommended for new design 5 lead to-220 (tha) horizontal 0.81(.032) 1.70 (.067) 6.81(.268) 1.40 (.055) 1.14 (.045) 5.84 (.230) 6.60 (.260) 6.83 (.269) 0.56 (.022) 0.36 (.014) 10.54 (.415) 9.78 (.385) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146) 1.68 (.066) typ 14.99 (.590) 14.22 (.560) 2.77 (.109) 2.29 (.090) 2.92 (.115) 4.83 (.190) 4.06 (.160) 2.87 (.113) 2.62 (.103) 5 lead to-220 (tva) vertical 1.68 (.066) typ 1.70 (.067) 7.51 (.296) 1.78 (.070) 4.34 (.171) 0.56 (.022) 0.36 (.014) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 14.99 (.590) 14.22 (.560) 2.92 (.115) 2.29 (.090) .94 (.037) .69 (.027) 8.64 (.340) 7.87 (.310) 6.80 (.268) 10.54 (.415) 9.78 (.385) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146)
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